1. Field of the Invention
The present invention relates to a patterning method in a semiconductor manufacturing process. In particular, this invention relates to a patterning method by forming a patterned layer, forming a sidewall spacer on sidewalls of the patterned layer so as to provide two-dimensional blocks on a base in a semiconductor manufacturing process.
2. Description of the Related Art
As the semiconductor manufacturing process has been continuously developed, the dimension of the integrated circuit element is smaller than 100 nm. Commonly, the higher the quantity of the electronic elements on a unit area of the wafer substrate is, the higher the efficiency is (the quantity is higher, the operation speed is faster, and the required power is lower). When the quantity of the electronic elements on a unit area of the wafer substrate is further increased, electronic elements with smaller dimensions are required so that the manufacturing process for enhancing the revolution needs to be developed. However, there will be a lot of bottlenecks on the manufacturing processes due to limitations for reducing the dimension of the elements.
Lithography is important for the IC production and the semiconductor manufacturing process development. Lithography can be improved by improving the optical technology to increase the resolution of the pattern transfer and reduce the critical dimension (CD). Thereby, the quantity of electronic elements on a unit area of the wafer substrate is increased.
Currently, optical lithography in semiconductor manufacturing processes has a dimension limitation. Due to the optical characteristic of the optics, the line width cannot be further reduced so that the resolution of the pattern transfer cannot be further improved. Moreover, when the dimension of the electronic elements become smaller, the overlay accuracy of the photolithography process cannot be controlled well. At the same time, the other lithography processes, such as E-beam lithography, EUV lithography etc., also has the development limitation on the throughput and the materials.
U.S. patent (US 2007/0249174), declared at 25 Oct. 2007, discloses a method for a patterned nano structure with different widths. First, a cap layer and a dummy layer are formed on a substrate. Next, patterns with different widths are pattern transferred on the dummy layer, and the left side wall and the right side wall of the dummy layer and the cap layer are etched. Then, spacers are formed on the left side wall and the right side wall of the dummy layer, and the dummy layer is removed and the spacers are reserved. By using the spacer as a sheltering mask, the etch process is performed to produce the nano structure with different widths. Although the US 2007/0249174 can produce the nano structure with different widths, it merely discloses the manufacturing method for a straight-line patterned structure.